An accurate and efficient gate level delay calculator for MOS circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Efficient Timing Analysis for CMOS Circuits Considering Data Dependent Delays
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Methods to improve digital MOS macromodel accuracy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Selection of Voltage Thresholds for Delay Measurement
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th annual Design Automation Conference
TA-PSV—Timing Analysis for Partially Specified Vectors
Journal of Electronic Testing: Theory and Applications
Temporal Properties of Self-Timed Rings
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Statistical gate delay model considering multiple input switching
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A unified framework for statistical timing analysis with coupling and multiple input switching
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
On bounding the delay of a critical path
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Algorithms for MIS vector generation and pruning
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A nonlinear cell macromodel for digital applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Statistical gate delay model for multiple input switching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Analytical model for the impact of multiple input switching noise on timing
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A "true" electrical cell model for timing, noise, and power grid verification
Proceedings of the 45th annual Design Automation Conference
Current source based standard cell model for accurate signal integrity and timing analysis
Proceedings of the conference on Design, automation and test in Europe
A false-path aware formal static timing analyzer considering simultaneous input transitions
Proceedings of the 46th Annual Design Automation Conference
Timed input pattern generation for an accurate delay calculation under multiple input switching
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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