The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
The Elmore delay as bound for RC trees with generalized input signals
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An accurate and efficient gate level delay calculator for MOS circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Advanced Engineering Mathematics: Maple Computer Guide
Advanced Engineering Mathematics: Maple Computer Guide
A multiple delay simulator for MOS LSI circuits
DAC '80 Proceedings of the 17th Design Automation Conference
AFTA: a formal delay model for functional thinking analysis
Proceedings of the conference on Design, automation and test in Europe
Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
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Since all physical devices have a finite non-zero responsetime, the notion of delay between the input and output logicsignals arises naturally once digital abstraction is done. Thisdelay should be positive and non-zero, since a physical devicetakes a finite amount of time to respond to the input. Defininga strictly positive delay is not a problem in the abstract domainof logic signals, since input and output ’’events‘‘ are preciselydefined. However, when the signal non-idealities are accountedfor, the notion of events is blurred and it is not obvious howto define delay such that it reflects the causal relationshipbetween the input and the output. By necessity, we define thestart and end points of these events by determining the timeinstants when the signals cross some appropriate voltage thresholds.The selection of these voltage thresholds for logic gates aswell as simple interconnect wires, is the subject of this paper.We begin by a discussion of what we mean by signal delay andhow it arises in a logic gate. With this background, startingfrom ideal inputs to ideal inverters and concluding with physicalinputs to physical inverters, we examine the problem of thresholdselection for inverters through a logical sequence of model refinement,using a combination of analytical and experimental techniques.Based on the insight gained through this analysis, we examinethe problem for multi-input (both static and dynamic) gates aswell as point-to-point interconnect wires. We show that thresholdsderived from the gate‘s DC voltage transfer characteristic removesthe anomalies, such as negative delay and large sensitivity toinput waveshape effects, that can arise with the widely used50% and 10%–90% thresholds. Despite its fundamentalnature, however, we note that the problem of threshold selectionhas received scant attention in the literature. To the best ofour knowledge, this is the first detailed study of this problem.