An accurate and efficient gate level delay calculator for MOS circuits

Authors:
Foong-Charn Chang;Chin-Fu Chen;Prasad Subramaniam
Affiliations:
-;-;-
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

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Abstract

This paper describes an accurate and efficient gate level delay calculator that automatically characterizes and computes the gate delays of MOS circuits. The high accuracy is attributed to a sophisticated delay model, which includes an accurate representation of the waveform, a consistent and meaningful definition of delay, a consideration of waveform slope effects at both the input and output of a gate, and an innovative approach for handling transmission gate circuits. Meanwhile, the high efficient delay characterization is accomplished through a fast timing simulation technique instead of using a circuit simulation or a timing simulation technique, a theorem to reduce a two-dimensional delay table into a scaled one-dimensional table, and an incremental characterization process.The delay calculator has been used in a production timing analyzer and a production multiple delay simulator since 1986. The results show that the multiple delay simulator performs 5000 times faster than a SPICE-like circuit simulator at only 15% cost of accuracy. Gate delay models, delay characterization, and practical examples are presented in this paper.