Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
An accurate and efficient gate level delay calculator for MOS circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Driver modeling and alignment for worst-case delay noise
Proceedings of the 38th annual Design Automation Conference
Hurwitz stable reduced order modeling for RLC interconnect trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Capturing crosstalk-induced waveform for accurate static timing analysis
Proceedings of the 2003 international symposium on Physical design
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of buffered hybrid structured clock networks
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Accurate delay computation for noisy waveform shapes
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A noniterative equivalent waveform model for timing analysis in presence of crosstalk
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Challenges in gate level modeling for delay and SI at 65nm and below
Proceedings of the 45th annual Design Automation Conference
A moment-based effective characterization waveform for static timing analysis
Proceedings of the 46th Annual Design Automation Conference
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This paper proposes a scheme that captures diverse input waveformsof CMOS gates for static timing analysis. Conventionallythe latest arrival time and transition time are calculated from thetimings when a transient waveform goes across pre-determinedreference voltages. However, this method cannot accurately considerthe impact of waveform shape on gate delay, when crosstalk-inducednon-monotonic waveforms or inductance-dominant stepwisewaveforms are injected. We propose a new timing analysisscheme called "equivalent waveform propagation". The proposedscheme calculates the equivalent waveform that makes the outputwaveform close to the actual waveform, and uses the equivalentwaveform for timing calculation. The proposed scheme can copewith various waveforms affected by resistive shielding, crosstalknoise, wire inductance etc. In this paper, we devise a method tocalculate equivalent waveform. The proposed calculation methodis compatible with conventional methods in gate delay library andcharacterization, and hence our method is easy to be implementedwith conventional static timing analysis tools.