Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Weibull Based Analytical Waveform Model
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Equivalent Waveform Propagation for Static Timing Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Accurate waveform modeling using singular value decomposition with applications to timing analysis
Proceedings of the 44th annual Design Automation Conference
A robust finite-point based gate model considering process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Compact modeling of variational waveforms
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing analysis with compact variation-aware standard cell models
Integration, the VLSI Journal
A moment-based effective characterization waveform for static timing analysis
Proceedings of the 46th Annual Design Automation Conference
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
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In this paper we present a new gate delay model for accurate modeling of difficult waveform shapes, such as those resulting from coupling capacitance noise, inductive ringing and resistive shielding. Our modeling approach uses a process of time shifting and time stretching of a set of so-called base-waveforms. These base-waveforms are selected from a large set of noisy waveform shapes that occur in interconnect structures with coupling and other types of noise, such that the delay error across all considered waveforms is minimized. Depending on the desired accuracy one or more base-waveforms can be used. This method is also used to model the gate output waveforms allowing for closure, in terms of the used base-waveforms across a circuit library. We show that the determination of the optimal set of base-waveforms under such input-to-output closure is exponential in complexity. We, therefore, propose an heuristic approach that maps the problem to the unate covering problem for which efficient solution methods are available. The new delay model can be applied in a timing analysis program with minor changes. We present results that demonstrate the accuracy of the new delay model for waveforms perturbed with noise for a large set of waveform shapes.