A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
WTA: waveform-based timing analysis for deep submicron circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
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ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Analytical modeling of crosstalk noise waveforms using Weibull function
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Accurate delay computation for noisy waveform shapes
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
Fast statistical circuit analysis with finite-point based transistor model
Proceedings of the conference on Design, automation and test in Europe
Accurate waveform modeling using singular value decomposition with applications to timing analysis
Proceedings of the 44th annual Design Automation Conference
Equivalent waveform propagation for static timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Weibull-based analytical waveform model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Finite-point-based transistor model: a new approach to fast circuit simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Integration, the VLSI Journal
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This paper proposes a robust gate model based on a finite-point modeling scheme. With current source model (CSM) framework, a robust, finite-point gate model is constructed. The new model depends on the selective points of I-V curves of gates. Thus, it implicitly incorporates the variation related parameters into finite points. In addition, to provide good accuracy on output waveform, the new model creates the input and output capacitance elements as nonlinear dependency on input/output waveform and process variation parameters. Experimental results show that the generated gate model has less than 3.7% error at mean, less than 6.2% error at variance and less than 5.8% at 90% percentile for cumulative density functions (CDFs).