Accurate waveform modeling using singular value decomposition with applications to timing analysis
Proceedings of the 44th annual Design Automation Conference
A robust finite-point based gate model considering process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Compact modeling of variational waveforms
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Efficient computation of current flow in signal wires for reliability analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Timing analysis with compact variation-aware standard cell models
Integration, the VLSI Journal
RDE-based transistor-level gate simulation for statistical static timing analysis
Proceedings of the 47th Design Automation Conference
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
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Current complimentary metal-oxide-semiconductor technologies are characterized by interconnect lines with increased relative resistance with respect to driver output resistance. Designs generate signal waveshapes that are very difficult to model using a single-parameter model such as the transition time. In this paper, we present a simple and robust two-parameter analytical expression for waveform modeling based on the Weibull cumulative distribution function. The Weibull model accurately captures the variety of waveshapes without introducing significant runtime overhead and produces results with less than 5% error. We also present a fast and simple algorithm to convert waveforms obtained by circuit simulation to the Weibull model. A methodology for characterizing gates for the new model is also presented. Simulation results for many single- and multiple-input gates show errors well below 5%. Our model can be used in a mixed environment where some signals may still be characterized by a single parameter.