A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variations

Authors:
Ken-Ichi Shinkai;Masanori Hashimoto;Takao Onoye
Affiliations:
Department of Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University, 1-5 Yamadaoka, Suita, Osaka, Japan;Department of Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University, 1-5 Yamadaoka, Suita, Osaka, Japan;Department of Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University, 1-5 Yamadaoka, Suita, Osaka, Japan
Venue:
Integration, the VLSI Journal
Year:
2013

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Abstract

This paper proposes a gate-delay model suitable for timing analysis that takes into consideration wide-ranging process-voltage-temperature (PVT) variations. The proposed model translates an output-current fluctuation due to PVT variations into modifications of the output load and input waveform. After translation, any conventional model can compute delay taking into account PVT variations by using the modified output load and reshaped input waveform. Experimental results with 90- and 45-nm technologies demonstrate that the average error of the fall and rise delay estimation in single- and multi-stage gates was approximately 5% on average over a wide range of input slews, output loads, and PVT variations. The proposed model can be used in Monte Carlo STA (static timing analysis) in addition to corner-based timing analysis. It can be also used in statistical STA to calculate the sensitivities of delays to variation parameters on-the-fly even when the nominal operating condition changes as well.