Empirical model-building and response surface
Empirical model-building and response surface
Measurement and modeling of MOS transistor current mismatch in analog IC's
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A performance optimization method by gate sizing using statistical static timing analysis
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A statistical static timing analysis considering correlations between delays
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A methodology to improve timing yield in the presence of process variations
Proceedings of the 41st annual Design Automation Conference
A Statistical Gate-Delay Model Considering Intra-Gate Variability
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimization objectives and models of variation for statistical gate sizing
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Understanding the effect of process variations on the delay of static and domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A dynamic method for efficient random mismatch characterization of standard cells
Proceedings of the International Conference on Computer-Aided Design
Integration, the VLSI Journal
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This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. Our model consists of a statistical transistor model and a gate-delay model. We present a modeling and extracting method of transistor characteristics for the intra-chip variability and the inter-chip variability. In the modeling of the intra-chip variability, it is important to consider a gate-size dependence by which the amount of intra-chip variation is affected. This effect is not captured in a statistical delay analysis reported so far. Our gate-delay model characterizes a statistical gate delay variation using a response surface method (RSM) according to the intra-chip and inter-chip variability of each transistor in a gate. We evaluate the accuracy of our model, and we show some simulated results of a circuit delay variation characterized by the measured variances of transistor currents.