Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Statistical Gate-Delay Model Considering Intra-Gate Variability
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A statistical gate delay model for intra-chip and inter-chip variabilities
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing using incremental parameterized statistical timing analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On the futility of statistical power optimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Evaluating statistical power optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Lithography-aware layout compaction
Proceedings of the great lakes symposium on VLSI
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This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exclusively on the optimization algorithms without considering the effects of the variation models and objective functions. This work empirically derives a simple variation model that is then used to optimize for robustness. Optimal results from example circuits used to study the effect of the statistical objective function on parametric yield.