Enhanced network flow algorithm for yield optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Leaf cell and hierarchical compaction techniques
Leaf cell and hierarchical compaction techniques
Symbolic layout compaction review
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Layout compaction for yield optimization via critical area minimization
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Fast optical and process proximity correction algorithms for integrated circuit manufacturing
Fast optical and process proximity correction algorithms for integrated circuit manufacturing
Optimization objectives and models of variation for statistical gate sizing
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
RADAR: RET-aware detailed routing using fast lithography simulations
Proceedings of the 42nd annual Design Automation Conference
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Predictive formulae for OPC with applications to lithography-friendly routing
Proceedings of the 45th annual Design Automation Conference
An algorithm for optimal two-dimensional compaction of VLSI layouts
Integration, the VLSI Journal
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Optical Proximity Correction (OPC) tools can suffer if the origi- nal layout is inherently difficult to print. Most routing techniques are unaware of the lithographic process, but several have been proposed to make the layout easier for the OPC tool to correct. This paper proposes a generalized preprocess step for OPC that uses a modified 1D layout compactor to expand or shrink geometry to decrease the amount of OPC work needed. This lithography-aware compactor estimates the OPC effort required and then uses a non-linear formulation to adjust the layout geometry. We describe a method for performing this compaction on small layouts and then extend it to handle larger hierarchical standard cell layouts.