Clock skew optimization via wiresizing for timing sign-off covering all process corners
Proceedings of the 46th Annual Design Automation Conference
PSTA-based branch and bound approach to the silicon speedpath isolation problem
Proceedings of the 2009 International Conference on Computer-Aided Design
Effective corner-based techniques for variation-aware IC timing verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Speedpath analysis under parametric timing models
Proceedings of the 47th Design Automation Conference
A unified multi-corner multi-mode static timing analysis engine
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Handling intra-die variations in PSTA
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
A fast approach for static timing analysis covering all PVT corners
Proceedings of the 48th Design Automation Conference
Unifying functional and parametric timing verification
Proceedings of the great lakes symposium on VLSI
Integration, the VLSI Journal
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Manufacturing process variations lead to circuit timing variability and a corresponding timing yield loss. Traditional corner analysis consists of checking all process corners (combinations of process parameter extremes) to make sure that circuit timing constraints are met at all corners, typically by running static timing analysis (STA) at every corner. This approach is becoming too expensive due to the increase in the number of corners with modern processes. As an alternative, we propose a linear-time approach for STA which covers all process corners in a single pass. Our technique assumes a linear dependence of delays and slews on process parameters and provides estimates of the worst case circuit delay and slew. It exhibits high accuracy in practice, and if the circuit has gates and relevant process parameters, the complexity of the algorithm is O(mn).