Convex Optimization
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Effective corner-based techniques for variation-aware IC timing verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
First-Order Incremental Block-Based Statistical Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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For integrated circuit (IC) fabrication technologies of 45nm and below, the impact of process variability in circuit performance is extremely relevant. Parametric static timing analysis (PSTA) techniques, whereby delays are modeled as affine functions of process parameters, were thus introduced to enable the computation of accurate timing estimates, accounting for process variability. Most often, only variations that occur between fabricated ICs (inter-die) are modeled, as the number of variables necessary to model such effects is manageable. Variations that occur across the same IC (intra-die) are usually neglected, as modeling them can add significant complexity to the model. This paper evaluates the impact of modeling intra-die variations in the context of PSTA and proposes effective techniques for handling them.