Proceedings of the 44th annual Design Automation Conference
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Variation-aware performance verification using at-speed structural test and statistical timing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An efficient method for statistical circuit simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Transistor-specific delay modeling for SSTA
Proceedings of the conference on Design, automation and test in Europe
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
Process variability-aware transient fault modeling and analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Tolerating process variations in high-level synthesis using transparent latches
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A Gaussian mixture model for statistical timing analysis
Proceedings of the 46th Annual Design Automation Conference
Non-Gaussian statistical timing analysis using second-order polynomial fitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and accurate statistical criticality computation under process variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast statistical analysis of process variation effects using accurate PLL behavioral models
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Proceedings of the 2009 International Conference on Computer-Aided Design
Process variation-aware performance analysis of asynchronous circuits
Microelectronics Journal
Statistical leakage estimation based on sequential addition of cell leakage currents
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing modeling for digital sub-threshold circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
iRetILP: an efficient incremental algorithm for min-period retiming under general delay model
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path criticality computation in parameterized statistical timing analysis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Fitting standard cell performance to generalized Lambda distributions
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Handling intra-die variations in PSTA
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Testability driven statistical path selection
Proceedings of the 48th Design Automation Conference
Interpolatory Projection Methods for Parameterized Model Reduction
SIAM Journal on Scientific Computing
Aging analysis at gate and macro cell level
Proceedings of the International Conference on Computer-Aided Design
Design dependent process monitoring for back-end manufacturing cost reduction
Proceedings of the International Conference on Computer-Aided Design
Journal of Electronic Testing: Theory and Applications
Unifying functional and parametric timing verification
Proceedings of the great lakes symposium on VLSI
Efficient statistical leakage analysis using deterministic cell leakage models
Microelectronics Journal
Eagle-eye: a near-optimal statistical framework for noise sensor placement
Proceedings of the International Conference on Computer-Aided Design
Uncertainty quantification for integrated circuits: stochastic spectral methods
Proceedings of the International Conference on Computer-Aided Design
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Variability in digital integrated circuits makes timing verification an extremely challenging task. In this paper, a canonical first-order delay model that takes into account both correlated and independent randomness is proposed. A novel linear-time block-based statistical timing algorithm is employed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form. At the end of the statistical timing, the sensitivity of all timing quantities to each of the sources of variation is available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature, which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in computer time, the probability of each edge or node of the timing graph being critical is computed. Numerical results are presented on industrial application-specified integrated circuit (ASIC) chips with over two million logic gates, and statistical timing results are compared to exhaustive corner analysis on a chip design whose hardware showed early mode timing violations