Automatic sizing of power/ground (P/G) networks in VLSI
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A threshold of ln n for approximating set cover
Journal of the ACM (JACM)
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Proceedings of the 2003 international symposium on Low power electronics and design
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Exploiting Resonant Behavior to Reduce Inductive Noise
Proceedings of the 31st annual international symposium on Computer architecture
Non-linear statistical static timing analysis for non-Gaussian variation sources
Proceedings of the 44th annual Design Automation Conference
Non-Gaussian statistical timing analysis using second-order polynomial fitting
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Statistical reliability analysis under process variation and aging effects
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate direct and indirect on-chip temperature sensing for efficient dynamic thermal management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Improved Thermal Tracking for Processors Using Hard and Soft Sensor Allocation Techniques
IEEE Transactions on Computers
PowerRush: a linear simulator for power grid
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 49th Annual Design Automation Conference
First-Order Incremental Block-Based Statistical Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
The relentless technology scaling has led to significantly reduced noise margin and complicated functionalities. As such, design time techniques per se are less likely to ensure power integrity, resulting in runtime voltage emergencies. To alleviate the issue, recently several works have shed light on the possibilities of dynamic noise management systems. Most of these works rely on on-chip noise sensors to accurately capture voltage emergencies. However, they all assume, either implicitly or explicitly, that the placement of the sensors is given. It remains an open problem in the literature how to optimally place a given number of noise sensors for best voltage emergency detection. In this paper, we formally define the problem of noise sensor placement along with a novel sensing quality metric (SQM) to be maximized. We then put forward an efficient algorithm to solve it, which is proved to be optimal in the class of polynomial complexity approximations. Experimental results on a set of industrial power grid designs show that compared with a simple average-noise based heuristic and two state-of-the-art temperature sensor placement algorithms aiming at recovering the full map or capturing the hot spots at all times, the proposed method on average can reduce the miss rate of voltage emergency detections by 7.4x, 15x and 6.2x, respectively.