Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise

Authors:
Takashi Enami;Shinyu Ninomiya;Masanori Hashimoto
Affiliations:
Department of Information Systems Engineering, Osaka University, Osaka, Japan;Department of Information Systems Engineering, Osaka University, Osaka, Japan;Department of Information Systems Engineering, Osaka University, Osaka, Japan
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2009

Citing 16
Cited 4

Analysis of performance impact caused by power supply noise in deep submicron devices

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits

Proceedings of the 38th annual Design Automation Conference
Path selection and pattern generation for dynamic timing analysis considering power supply noise effects

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A stochastic approach To power grid analysis

Proceedings of the 41st annual Design Automation Conference
First-order incremental block-based statistical timing analysis

Proceedings of the 41st annual Design Automation Conference
Worst-case circuit delay taking into account power supply variations

Proceedings of the 41st annual Design Automation Conference
Fast flip-chip power grid analysis via locality and grid shells

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing analysis considering spatial power/ground level variation

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing analysis considering temporal supply voltage fluctuation

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Static timing analysis considering power supply variations

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Stochastic variational analysis of large power grids considering intra-die correlations

Proceedings of the 43rd annual Design Automation Conference
Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits

MTV '06 Proceedings of the Seventh International Workshop on Microprocessor Test and Verification
Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise

Proceedings of the 2008 international symposium on Physical design
Statistical timing analysis under spatial correlations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Extraction of Spatial Correlation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

On-chip power supply noise and its implications on timing

Proceedings of the 20th symposium on Great lakes symposium on VLSI
Timing yield analysis considering process-induced temperature and supply voltage variations

Microelectronics Journal
A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variations

Integration, the VLSI Journal
Eagle-eye: a near-optimal statistical framework for noise sensor placement

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.03

Visualization

Abstract

Power supply noise is having increasingly more influence on timing, even though noise-aware timing analysis has not yet been fully established, because of several difficulties such as its dependence on input vectors and dynamic behavior. This paper proposes static timing analysis that takes power supply noise into consideration where the dependence of noise on input vectors and spatial and temporal correlations are handled statistically. We construct a statistical model of power supply voltage that dynamically varies with spatial and temporal correlation, and represent it as a set of uncorrelated variables. We demonstrate that power-voltage variations are highly correlated and adopting principal component analysis as an orthogonalization technique can effectively reduce the number of variables. Experiments confirmed the validity of our model and the accuracy of timing analysis. We also discuss the accuracy and CPU time in association with the reduced number of variables.