Timing analysis with compact variation-aware standard cell models
Integration, the VLSI Journal
Statistical static timing analysis considering leakage variability in power gated designs
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing yield analysis considering process-induced temperature and supply voltage variations
Microelectronics Journal
Power yield analysis under process and temperature variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.03 |
We propose a scalable efficient parameterized block-based statistical static timing analysis (SSTA) algorithm incorporating both Gaussian and non-Gaussian parameter distributions, capturing spatial correlations using a grid-based model. As a preprocessing step, we employ an independent component analysis to transform the set of correlated non-Gaussian parameters to a basis set of parameters that are statistically independent. Given the moments of the variational parameters, we use a Pade acute-approximation-based moment-matching scheme to generate the distributions of the random variables representing the signal arrival times and preserve correlation information by propagating arrival times in a canonical form. Our SSTA procedure is able to generate the circuit delay distributions with reasonably small prediction errors. For the ISCAS89 benchmark circuits, as compared to Monte Carlo simulations, we obtain average errors of 0.99%, 2.05%, 2.33%, and 2.36%, respectively, in the mean, standard deviation, and 5% and 95% quantile points of the circuit delay. Experimental results show that our procedure can handle as many as 256 correlated non-Gaussian variables in about 5 min of runtime. For a circuit with |G| gates and a layout with g spatial correlation grids, the complexity of our approach is O(g|G|) .