First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Static timing analysis considering power supply variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Parametric yield analysis and optimization in leakage dominated technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PERT as an aid to logic design
IBM Journal of Research and Development
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis and verification of power grids considering process-induced leakage-current variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Extraction of Spatial Correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Thermal Profile Considering Process Variations: Analysis and Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design-Specific Optimization Considering Supply and Threshold Voltage Variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Process variations cause fluctuations in the threshold voltage of integrated circuits (ICs). The variations, in turn, lead to uncertainties in the leakage current, drawn off the power grid that the underlying circuit is connected to. Because of the interdependency between the leakage power and temperature, process variations impose statistical behavior on the nodes' supply voltage and also on the temperature. In addition, the resistivity of the interconnects increases with temperature. Consequently, the imposed variations significantly impact the performance of devices and interconnects. This paper presents a statistical analysis of the timing yield by taking into account both the process and environmental variations. By considering the statistical profile of the temperature and supply voltage, the process variations are mapped to the delay variations across a die. This helps to accurately estimate the timing yield and check the robustness of the circuits early in the design process and avoid over-design. Monte-Carlo simulations on ISCAS89 benchmarks verify the accuracy of the proposed methodology.