A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Model and analysis for combined package and on-chip power grid simulation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Consistent placement of macro-blocks using floorplanning and standard-cell placement
Proceedings of the 2002 international symposium on Physical design
A static pattern-independent technique for power grid voltage integrity verification
Proceedings of the 40th annual Design Automation Conference
Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
The impact of variability on power
Proceedings of the 2004 international symposium on Low power electronics and design
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ISPD placement contest updates and ISPD 2007 global routing contest
Proceedings of the 2007 international symposium on Physical design
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Designing and optimizing compute kernels on NVIDIA GPUs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Statistical analysis of large on-chip power grid networks by variational reduction scheme
Integration, the VLSI Journal
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation
Proceedings of the 47th Design Automation Conference
Efficient simulation of power grids
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Efficient power grid integrity analysis using on-the-fly error check and reduction
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Acceleration of random-walk-based linear circuit analysis using importance sampling
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
2011 TAU power grid simulation contest: benchmark suite and results
Proceedings of the International Conference on Computer-Aided Design
Fast static analysis of power grids: algorithms and implementations
Proceedings of the International Conference on Computer-Aided Design
Power grid analysis and verification considering temperature variations
Microelectronics Journal
A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Minimizing power supply noise through harmonic mappings in networks-on-chip
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Timing yield analysis considering process-induced temperature and supply voltage variations
Microelectronics Journal
Proceedings of the International Conference on Computer-Aided Design
Deterministic random walk preconditioning for power grid analysis
Proceedings of the International Conference on Computer-Aided Design
2012 TAU power grid simulation contest: benchmark suite and results
Proceedings of the International Conference on Computer-Aided Design
Parallel forward and back substitution for efficient power grid simulation
Proceedings of the International Conference on Computer-Aided Design
Benchmarking for research in power delivery networks of three-dimensional integrated circuits
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Incorporating the impacts of workload-dependent runtime variations into timing analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
ABCD-L: approximating continuous linear systems using boolean models
Proceedings of the 50th Annual Design Automation Conference
Scalable vectorless power grid current integrity verification
Proceedings of the 50th Annual Design Automation Conference
The impact of electromigration in copper interconnects on power grid integrity
Proceedings of the 50th Annual Design Automation Conference
Power yield analysis under process and temperature variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Redundancy-aware electromigration checking for mesh power grids
Proceedings of the International Conference on Computer-Aided Design
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Benchmarks are an immensely useful tool in performing research since they allow for rapid and clear comparison between different approaches to solving CAD problems. Recent experience from the placement [1] and routing [2] areas suggests that the ready availability of realistic industrial-size benchmarks can energize research in a given area, and can even lead to significant breakthroughs. To this end, we are making a number of power grid analysis benchmarks available for the public. These are all drawn from real designs, and vary over a reasonable range of size and difficulty thereby making studies of algorithm complexity possible. This paper documents the format for the various benchmarks, and give details for their access.