Model Problems for the Multigrid Optimization of Systems Governed by Differential Equations
SIAM Journal on Scientific Computing
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Incremental partitioning-based vectorless power grid verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Electronic Circuit & System Simulation Methods (SRE)
Electronic Circuit & System Simulation Methods (SRE)
Fast vectorless power grid verification using an approximate inverse technique
Proceedings of the 46th Annual Design Automation Conference
Proceedings of the 47th Design Automation Conference
An efficient dual algorithm for vectorless power grid verification under linear current constraints
Proceedings of the 47th Design Automation Conference
Early P/G grid voltage integrity verification
Proceedings of the International Conference on Computer-Aided Design
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parallel On-Chip Power Distribution Network Analysis on Multi-Core-Multi-GPU Platforms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Overview of vectorless/early power grid verification
Proceedings of the International Conference on Computer-Aided Design
Large-scale flip-chip power grid reduction with geometric templates
Proceedings of the Conference on Design, Automation and Test in Europe
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To deal with the growing phenomenon of electromigration (EM), power grid current integrity verification becomes indispensable to designing reliable power delivery networks (PDNs). Unlike previous works that focus on vectorless voltage integrity verification of power grids, in this work, for the first time we present a scalable vectorless power grid current integrity verification framework. By taking advantage of multilevel power grid verifications, large-scale power grid current integrity verification tasks can be achieved in a very efficient way. Additionally, a novel EM-aware geometric power grid reduction method is proposed to well preserve the similar geometric and electrical properties of the original grid on the coarse-level power grids, which allows to quickly identify the potential "hot wires" that may carry greater-than-desired currents in a given power grid design. The proposed multilevel power grid verification algorithm provides flexible tradeoffs between the current integrity verification cost and solution quality, while the desired upper/lower bounds for worst case currents flowing through a wire can also be computed efficiently. Extensive experimental results show that our current integrity verification approach can efficiently handle very large power grid designs with good solution quality.