Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Full-chip verification methods for DSM power distribution systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hierarchical analysis of power distribution networks
Proceedings of the 37th Annual Design Automation Conference
Electronic Circuit & System Simulation Methods (SRE)
Electronic Circuit & System Simulation Methods (SRE)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Early-stage power grid analysis for uncertain working modes
Proceedings of the 2004 international symposium on Physical design
Worst-case circuit delay taking into account power supply variations
Proceedings of the 41st annual Design Automation Conference
Power grid voltage integrity verification
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Floorplan and power/ground network co-synthesis for fast design convergence
Proceedings of the 2006 international symposium on Physical design
SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fill
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Incremental partitioning-based vectorless power grid verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Static timing analysis considering power supply variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Precise identification of the worst-case voltage drop conditions in power grid verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Efficient representation and analysis of power grids
Proceedings of the conference on Design, automation and test in Europe
Context-sensitive static transistor-level IR analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Generating realistic stimuli for accurate power grid analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast vectorless power grid verification using an approximate inverse technique
Proceedings of the 46th Annual Design Automation Conference
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs
Proceedings of the 2009 International Conference on Computer-Aided Design
An efficient dual algorithm for vectorless power grid verification under linear current constraints
Proceedings of the 47th Design Automation Conference
Efficient simulation of power grids
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
More realistic power grid verification based on hierarchical current and power constraints
Proceedings of the 2011 international symposium on Physical design
Floorplanning considering IR drop in multiple supply voltages island designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient incremental analysis of on-chip power grid via sparse approximation
Proceedings of the 48th Design Automation Conference
Power grid verification using node and branch dominance
Proceedings of the 48th Design Automation Conference
Power grid correction using sensitivity analysis under an RC model
Proceedings of the 48th Design Automation Conference
Vectorless verification of RLC power grids with transient current constraints
Proceedings of the International Conference on Computer-Aided Design
A hierarchical matrix inversion algorithm for vectorless power grid verification
Proceedings of the International Conference on Computer-Aided Design
Power grid correction using sensitivity analysis
Proceedings of the International Conference on Computer-Aided Design
Early P/G grid voltage integrity verification
Proceedings of the International Conference on Computer-Aided Design
Incremental power grid verification
Proceedings of the 49th Annual Design Automation Conference
Power grid effects and their impact on-die
Proceedings of the International Conference on Computer-Aided Design
Overview of vectorless/early power grid verification
Proceedings of the International Conference on Computer-Aided Design
Constraint abstraction for vectorless power grid verification
Proceedings of the 50th Annual Design Automation Conference
Modeling and analysis of power distribution networks in 3-D ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A vectorless framework for power grid electromigration checking
Proceedings of the International Conference on Computer-Aided Design
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Design verification must include the power grid. Checking that the voltage on the power grid does not drop by more than some critical threshold is a very difficult problem, for at least two reasons: i) the obviously large size of the power grids for modern high-performance chips, and ii) the difficulty of setting up the right simulation conditions for the power grid that provide some measure of a realistic worst case voltage drop. The huge number of possible circuit operational modes or workloads makes it impossible to do exhaustive analysis. We propose a static technique for power grid verification, where static is in the sense of static timing analysis, meaning that it does not depend on, nor require, user-specified stimulus to drive a simulation. The verification is posed as an optimization problem under user-supplied current constraints. We propose that current constraints are the right kind of abstraction to use in order to develop a practical methodology for power grid verification. We present our verification approach, and report on the results of applying it to a number of test-case power grids.