Parallel Preconditioning with Sparse Approximate Inverses
SIAM Journal on Scientific Computing
A static pattern-independent technique for power grid voltage integrity verification
Proceedings of the 40th annual Design Automation Conference
Power grid voltage integrity verification
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A geometric approach for early power grid verification using current constraints
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Fast vectorless power grid verification using an approximate inverse technique
Proceedings of the 46th Annual Design Automation Conference
An efficient dual algorithm for vectorless power grid verification under linear current constraints
Proceedings of the 47th Design Automation Conference
Overview of vectorless/early power grid verification
Proceedings of the International Conference on Computer-Aided Design
Constraint abstraction for vectorless power grid verification
Proceedings of the 50th Annual Design Automation Conference
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The verification of power grids in modern integrated circuits must start early in the design process when adjustments can be most easily incorporated. This work describes a vectorless verification technique that deals with circuit uncertainty in the framework of current constraints. In such a framework, grid verification becomes a question of computing the worst-case voltage drops which, in turn, entails the solution of as many linear programs (LPs) as there are nodes. First, we extend grid verification to also check for the worst-case branch currents. We show that this would require as many LPs as there are branches. Second, we propose a starkly different approach to reduce the number of LPs in the verification problem. We achieve this by examining dominance relations among node voltage drops and among branch currents. This allows us to replace a group of LPs by one conservative and tight LP. Results show a dramatic reduction in the number of LPs thus making vectorless grid verification in the framework of current constraints practical and scalable.