A static pattern-independent technique for power grid voltage integrity verification
Proceedings of the 40th annual Design Automation Conference
Incremental partitioning-based vectorless power grid verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Handling inductance in early power grid verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A geometric approach for early power grid verification using current constraints
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Fast vectorless power grid verification using an approximate inverse technique
Proceedings of the 46th Annual Design Automation Conference
An efficient dual algorithm for vectorless power grid verification under linear current constraints
Proceedings of the 47th Design Automation Conference
More realistic power grid verification based on hierarchical current and power constraints
Proceedings of the 2011 international symposium on Physical design
Power grid verification using node and branch dominance
Proceedings of the 48th Design Automation Conference
Vectorless verification of RLC power grids with transient current constraints
Proceedings of the International Conference on Computer-Aided Design
A hierarchical matrix inversion algorithm for vectorless power grid verification
Proceedings of the International Conference on Computer-Aided Design
Early P/G grid voltage integrity verification
Proceedings of the International Conference on Computer-Aided Design
Incremental power grid verification
Proceedings of the 49th Annual Design Automation Conference
Fast Vectorless Power Grid Verification Under an RLC Model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dual Algorithms for Vectorless Power Grid Verification Under Linear Current Constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Vectorless power grid verification is a formal approach to analyze power supply noises across the chip without detailed current waveforms. It is typically formulated and solved as linear programs, which demand intensive computational power, especially for large-scale power grids. In this paper, we propose a constraint abstraction technique to reduce the computation cost of vectorless verification. The boundary condition of a subgrid is modeled by boundary constraints, which enable efficient calculation of conservative bounds of power supply noises in a divide-and-conquer manner. Experimental results show that the proposed approach achieves significant speedup over prior art while maintaining good solution quality.