A static pattern-independent technique for power grid voltage integrity verification
Proceedings of the 40th annual Design Automation Conference
Electronic Circuit & System Simulation Methods (SRE)
Electronic Circuit & System Simulation Methods (SRE)
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate power grid analysis with behavioral transistor network modeling
Proceedings of the 2007 international symposium on Physical design
Handling inductance in early power grid verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Early power grid verification under circuit current uncertainties
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A geometric approach for early power grid verification using current constraints
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Fast vectorless power grid verification using an approximate inverse technique
Proceedings of the 46th Annual Design Automation Conference
Verification and codesign of the package and die power delivery system using wavelets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power grid verification using node and branch dominance
Proceedings of the 48th Design Automation Conference
Power grid correction using sensitivity analysis under an RC model
Proceedings of the 48th Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
Power grid analysis and verification considering temperature variations
Microelectronics Journal
Incremental power grid verification
Proceedings of the 49th Annual Design Automation Conference
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Full-chip verification requires one to check if the power grid is safe, i.e., if the voltage drop on the grid does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally expensive, because of the large variety of possible circuit behaviors that would need to be simulated; it also has the disadvantage that it requires full knowledge of the details of the circuit attached to the grid, thereby precluding early verification of the grid. We propose a power grid verification technique that can be applied before the complete circuit has been designed and without exact knowledge of the circuit currents. We use current constraints, which are upper bound constraints on the currents that can be drawn from the grid, as a way to capture the uncertainty about the circuit details and activity. Based on this, we propose two solution approaches. One approach gives an upper-bound on the worst-case voltage drop at every node of the grid. Another, less expensive approach, applies a sufficient condition (thus, this becomes a conservative approach) to check if the drop on the grid exceeds a given voltage threshold