A floorplan-based planning methodology for power and clock distribution in ASICs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Fast power/ground network optimization based on equivalent circuit modeling
Proceedings of the 38th annual Design Automation Conference
Random walks in a supply network
Proceedings of the 40th annual Design Automation Conference
A static pattern-independent technique for power grid voltage integrity verification
Proceedings of the 40th annual Design Automation Conference
Efficient power/ground network analysis for power integrity-driven design methodology
Proceedings of the 41st annual Design Automation Conference
Supply Voltage Degradation Aware Analytical Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Floorplan and power/ground network co-synthesis for fast design convergence
Proceedings of the 2006 international symposium on Physical design
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Power Delivery Aware Floorplanning for Voltage Island Designs
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Heuristic power/ground network and floorplan co-design method
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Implementation and extensibility of an analytic placer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal-aware cell and through-silicon-via co-placement for 3D ICs
Proceedings of the 48th Design Automation Conference
Statistical thermal modeling and optimization considering leakage power variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Excessive supply voltage drops in a circuit may lead to significant circuit performance degradation and even malfunction. To handle this problem, existing power delivery aware placement algorithms model voltage drops as an optimization objective. We observe that directly minimizing voltage drops in an objective function might not resolve voltage-drop violations and might even cause problems in power-integrity convergence. To remedy this deficiency, in this paper, we propose new techniques to incorporate device power spreading forces into a mixed-size analytical placement framework. Unlike the state-of-the-art previous work that handles the worst voltage-drop spots one by one, our approach simultaneously and globally spreads all the blocks with voltage-drop violations to desired locations directly to minimize the violations. To apply the power force, we model macro current density and power rails for our placement framework to derive desired macro/cell locations. To further improve the solution quality, we propose an efficient mathematical transformation to adjust the power force direction and magnitude. Experimental results show that our approach can substantially improve the voltage drops, wirelength, and runtime over the previous work.