APlace: a general analytic placement framework
Proceedings of the 2005 international symposium on Physical design
Supply Voltage Degradation Aware Analytical Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Seeing the forest and the trees: Steiner wirelength optimization in placemen
Proceedings of the 2006 international symposium on Physical design
A faster implementation of APlace
Proceedings of the 2006 international symposium on Physical design
Lens aberration aware timing-driven placement
Proceedings of the conference on Design, automation and test in Europe: Proceedings
X-architecture placement based on effective wire models
Proceedings of the 2007 international symposium on Physical design
Fast and robust quadratic placement combined with an exact linear net model
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fast and accurate routing demand estimation for efficient routability-driven placement
Proceedings of the conference on Design, automation and test in Europe
Metal-density driven placement for cmp variation and routability
Proceedings of the 2008 international symposium on Physical design
Abacus: fast legalization of standard cell circuits with minimal movement
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 45th annual Design Automation Conference
An integrated nonlinear placement framework with congestion and porosity aware buffer planning
Proceedings of the 45th annual Design Automation Conference
Lens aberration aware placement for timing yield
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Guiding global placement with wire density
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Stochastic power/ground supply voltage prediction and optimization via analytical placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Spare-cell-aware multilevel analytical placement
Proceedings of the 46th Annual Design Automation Conference
A rigorous framework for convergent net weighting schemes in timing-driven placement
Proceedings of the 2009 International Conference on Computer-Aided Design
A study of routability estimation and clustering in placement
Proceedings of the 2009 International Conference on Computer-Aided Design
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs
Proceedings of the 2009 International Conference on Computer-Aided Design
StarPlace: A new analytic method for FPGA placement
Integration, the VLSI Journal
Post sign-off leakage power optimization
Proceedings of the 48th Design Automation Conference
TSV-aware analytical placement for 3D IC designs
Proceedings of the 48th Design Automation Conference
Ripple: an effective routability-driven placer by iterative cell movement
Proceedings of the International Conference on Computer-Aided Design
Mixed integer programming models for detailed placement
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
MAPLE: multilevel adaptive placement for mixed-size designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Structure-aware placement for datapath-intensive circuit designs
Proceedings of the 49th Annual Design Automation Conference
SRP: simultaneous routing and placement for congestion refinement
Proceedings of the 2013 ACM international symposium on International symposium on physical design
An efficient and effective analytical placer for FPGAs
Proceedings of the 50th Annual Design Automation Conference
Ripple 2.0: high quality routability-driven placement via global router integration
Proceedings of the 50th Annual Design Automation Conference
In-placement clock-tree aware multi-bit flip-flop generation for power optimization
Proceedings of the International Conference on Computer-Aided Design
Techniques for scalable and effective routability evaluation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Automated cell placement is a critical problem in very large scale integration (VLSI) physical design. New analytical placement methods that simultaneously spread cells and optimize wirelength have recently received much attention from both academia and industry. A novel and simple objective function for spreading cells over the placement area is described in the patent of Naylor et al. (U.S. Pat. 6301693). When combined with a wirelength objective function, this allows efficient simultaneous cell spreading and wirelength optimization using nonlinear optimization techniques. In this paper, we implement an analytic placer (APlace) according to these ideas (which have other precedents in the open literature), and conduct in-depth analysis of characteristics and extensibility of the placer. Our contributions are as follows. 1) We extend the objective functions described in (Naylor et al., U.S. Patent 6301693) with congestion information and implement a top-down hierarchical (multilevel) placer (APlace) based on them. For IBM-ISPD04 circuits, the half-perimeter wirelength of APlace outperforms that of FastPlace, Dragon, and Capo, respectively, by 7.8%, 6.5%, and 7.0% on average. For eight IBM-PLACE v2 circuits, after the placements are detail-routed using Cadence WRoute, the average improvement in final wirelength is 12.0%, 8.1%, and 14.1% over QPlace, Dragon, and Capo, respectively. 2) We extend the placer to address mixed-size placement and achieve an average of 4% wirelength reduction on ten ISPD'02 mixed-size benchmarks compared to results of the leading-edge solver, FengShui. 3) We extend the placer to perform timing-driven placement. Compared with timing-driven industry tools, evaluated by commercial detailed routing and static timing analysis, we achieve an average of 8.4% reduction in cycle time and 7.5% reduction in wirelength for a set of six industry testcases. 4) We also extend the placer to perform input/output-core coplacement and constraint handing for mixed-signal designs. Our paper aims to, and empirically demonstrates, that the APlace framework is a general, and extensible platform for "spatial embedding" tasks across many aspects of system physical implementation.