PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Estimation of maximum current envelope for power bus analysis and design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hierarchical analysis of power distribution networks
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
Attractor-repeller approach for global placement
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Decoupling capacitance allocation for power supply noise suppression
Proceedings of the 2001 international symposium on Physical design
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
Proceedings of the 2002 international symposium on Physical design
FAR: fixed-points addition & relaxation based placement
Proceedings of the 2002 international symposium on Physical design
Design Automation for Timing-Driven Layout Synthesis
Design Automation for Timing-Driven Layout Synthesis
Simulation and optimization of the power distribution network in VLSI circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Frequency domain analysis of switching noise on power supply network
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Random walks in a supply network
Proceedings of the 40th annual Design Automation Conference
Switching activity estimation of VLSI circuits using Bayesian networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2004 international symposium on Physical design
Optimal placement of power supply pads and pins
Proceedings of the 41st annual Design Automation Conference
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
APlace: a general analytic placement framework
Proceedings of the 2005 international symposium on Physical design
Partitioning-based approach to fast on-chip decap budgeting and minimization
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Floorplanning with power supply noise avoidance
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Decoupling capacitors for multi-voltage power distribution systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implementation and extensibility of an analytic placer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient algorithms for fast IR drop analysis exploiting locality
Integration, the VLSI Journal
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Increasingly significant power/ground (P/G) supply voltage degradation in nanometer VLSI designs leads to system performance degradation and even malfunction, which requires stochastic analysis and optimization techniques. We represent the supply voltage degradation at a P/G node as a function of the supply currents and the effective resistance of a P/G supply network and propose an efficient stochastic system-level P/G supply voltage prediction method, which computes P/G supply network effective resistances in a random walk process. We further propose to reduce P/G supply voltage degradation via placement of supply current sources, and integrate P/G supply voltage degradation reduction with conventional placement objectives in an analytical placement framework. Our experimental results show that the proposed stochastic P/G supply network prediction method achieves 10×-100× speedup compared with traditional SPICE simulation, and the proposed P/G supply voltage degradation aware placement achieves an average of 20.9% (11.7%) reduction on maximum (average) supply voltage degradation with only 4.3 % wirelength increase.