Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Attractor-repeller approach for global placement
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Provably good global buffering using an available buffer block plan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Efficient and effective placement for very large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implementation and extensibility of an analytic placer
Proceedings of the 2004 international symposium on Physical design
Proceedings of the 2004 international symposium on Physical design
Unified quadratic programming approach for mixed mode placement
Proceedings of the 2005 international symposium on Physical design
The ISPD2005 placement contest and benchmark suite
Proceedings of the 2005 international symposium on Physical design
mFAR: fixed-points-addition-based VLSI placement algorithm
Proceedings of the 2005 international symposium on Physical design
Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Supply Voltage Degradation Aware Analytical Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Multilevel expansion-based VLSI placement with blockages
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Engineering details of a stable force-directed placer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Mixed-size placement via line search
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Fast and robust quadratic placement combined with an exact linear net model
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Timing-driven placement for heterogeneous field programmable gate array
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
DPlace2.0: a stable and efficient analytical placement based on diffusion
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Lens aberration aware placement for timing yield
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Stochastic power/ground supply voltage prediction and optimization via analytical placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SimPL: an effective placement algorithm
Proceedings of the International Conference on Computer-Aided Design
SimPL: an algorithm for placing VLSI circuits
Communications of the ACM
| Hi-index | 0.02 |
In this paper we describe the Fixed-points Addition and Relaxation(FAR) based placement technique. Fixed point is a pseudo cellconnected to a movable cell. By introducing fixed points, theplacement can be maintained in a force equilibrium state andfurther transformed into another equilibrium state. By relaxingsome of the previously introduced fixed points, we can partially orcompletely collapse the current placement in order to repositionthe cells, or incrementally perturb the existing good solution tofulfill additional requirements. We apply the FAR-based approach toglobal placement for total wire length minimization, and toincremental placement for Buffer Site Generation (BSG). For globalplacement, our experimental results show that the FAR methodachieves 54.4% CPU speedup and total wire length comparable to thatachieved by the constant force based approach [1]. Experimentalresults indicate that to accommodate buffers in specific regions,FAR is able to perturb incrementally a given solution in awell-controlled way.