Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Delay bounded buffered tree construction for timing driven floorplanning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Routability-driven repeater block planning for interconnect-centric floorplanning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Routing tree construction under fixed buffer locations
Proceedings of the 37th Annual Design Automation Conference
Repeater block planning under simultaneous delay and transition time constraints
Proceedings of the conference on Design, automation and test in Europe
Provably good global buffering by multi-terminal multicommodity flow approximation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Integrated power supply planning and floorplanning
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Routability driven floorplanner with buffer block planning
Proceedings of the 2002 international symposium on Physical design
Buffer insertion with adaptive blockage avoidance
Proceedings of the 2002 international symposium on Physical design
FAR: fixed-points addition & relaxation based placement
Proceedings of the 2002 international symposium on Physical design
Buffer block planning for interconnect planning and prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
An algorithm for integrated pin assignment and buffer planning
Proceedings of the 39th annual Design Automation Conference
Effects of global interconnect optimizations on performance estimation of deep submicron design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Provably good global buffering using an available buffer block plan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An integrated floorplanning with an efficient buffer planning algorithm
Proceedings of the 2003 international symposium on Physical design
Practical Approximation Algorithms for Separable Packing Linear Programs
WADS '01 Proceedings of the 7th International Workshop on Algorithms and Data Structures
Repeater and current-sensing hybrid circuits for on-chip interconnects
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Dynamic global buffer planning optimization based on detail block locating and congestion analysis
Proceedings of the 40th annual Design Automation Conference
Multilevel floorplanning/placement for large-scale modules using B*-trees
Proceedings of the 40th annual Design Automation Conference
Improved a priori terconnect predictions and technology extrapolation in the GTX system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Fast Hierarchical Floorplanning with Congestion and Timing Control
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
On finding an empty staircase polygon of largest area (width) in a planar point-set
Computational Geometry: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2004 international workshop on System level interconnect prediction
A fast algorithm for identifying good buffer insertion candidate locations
Proceedings of the 2004 international symposium on Physical design
Power macromodeling of global interconnects considering practical repeater insertion
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Practical repeater insertion for low power: what repeater library do we need?
Proceedings of the 41st annual Design Automation Conference
Modeling repeaters explicitly within analytical placement
Proceedings of the 41st annual Design Automation Conference
Simultaneous Analytic Area and Power Optimization for Repeater Insertion
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A buffer planning algorithm with congestion optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Buffer allocation algorithm with consideration of routing congestion
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Interconnect Planning with Local Area Constrained Retiming
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Low-power on-chip communication based on transition-aware global signaling (TAGS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Buffer Planning Algorithm Based on Partial Clustered Floorplanning
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A sensitivity analysis of low-power repeater insertion
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Net weighting to reduce repeater counts during placement
Proceedings of the 42nd annual Design Automation Conference
An algorithm for integrated pin assignment and buffer planning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accurate estimation of global buffer delay within a floorplan
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
The scaling of interconnect buffer needs
Proceedings of the 2006 international workshop on System-level interconnect prediction
Fast buffer planning and congestion optimization in interconnect-driven floorplanning
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Noise-aware buffer planning for interconnect-driven floorplanning
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Simultaneous floorplanning and buffer block planning
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A buffer planning algorithm based on dead space redistribution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Buffering global interconnects in structured ASIC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Clustering for processing rate optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Hierarchical partitioning of VLSI floorplans by staircases
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Improved timing closure by early buffer planning in floor-placement design flow
Proceedings of the 17th ACM Great Lakes symposium on VLSI
An effective buffer planning algorithm for IP based fixed-outline SOC placement
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Journal of Electronic Testing: Theory and Applications
Buffering global interconnects in structured ASIC design
Integration, the VLSI Journal
Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microarchitecture configurations and floorplanning co-optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Reducing interconnect delay uncertainty via hybrid polarity repeater insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Incremental buffer insertion and module resizing algorithm using geometric programming
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Clustering for processing rate optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Handling routability in floorplan design with twin binary trees
Integration, the VLSI Journal
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
Proceedings of the 46th Annual Design Automation Conference
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Differential current-sensing for on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Buffer planning for IP placement using sliced-LFF
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Floorplanning method based on liner programming
ICS'06 Proceedings of the 10th WSEAS international conference on Systems
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new buffer planning algorithm based on room resizing
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer insertion, and derive closed-form formula for FR. We observe that the FR for a buffer is quite large in general even under fairly tight delay constraint. Therefore, FR gives us a lot of flexibility to plan for buffer locations. We then develop an effective buffer block planning (BBP) algorithm to perform buffer clustering such that the overall chip area and the buffer block number can be minimized. To the best of our knowledge, this is the first in-depth study on buffer planning for interconnect-driven floorplanning with both area and delay consideration.