Modeling the influence of multilevel interconnect on chip performance
Modeling the influence of multilevel interconnect on chip performance
Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GTX: the MARCO GSRC technology extrapolation system
Proceedings of the 37th Annual Design Automation Conference
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
System level interconnect design for network-on-chip using interconnect IPs
Proceedings of the 2003 international workshop on System-level interconnect prediction
aSOC: A Scalable, Single-Chip Communications Architecture
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MAIA: a framework for networks on chip generation and verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnects
International Journal of High Performance Systems Architecture
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
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Performance and power of on-chip interconnects in the nanometer realm have been an increasing source of concern to designers. Network-on-Chip (NoC)structures have been proposed as a solution to achieve efficient and reliable communication. Even with the regularity of NoC structures, it is important for designers to acknowledge the physical layer interconnect issues to plan and quantify achievable performance. In this paper we present a spice-based tool: No-CIC: Network-on-Chip Interconnect Calculator, which enables NoC designers to assess the impact of interconnect circuit designs and understand the tradeoffs involved to achieve better a priori planning. NoCIC determines the interconnect performance and power based on select NoC and circuit parameters. The effects of each parameter on the interconnect performance and power are expressed through various two-dimensional and three-dimensional plots.