System level interconnect design for network-on-chip using interconnect IPs

Authors:
Jian Liu;Meigen Shen;Li-Rong Zheng;Hannu Tenhunen
Affiliations:
Royal Institute of Technology (KTH), Kista, Stockholm, Sweden;Royal Institute of Technology (KTH), Kista, Stockholm, Sweden;Royal Institute of Technology (KTH), Kista, Stockholm, Sweden;Royal Institute of Technology (KTH), Kista, Stockholm, Sweden
Venue:
Proceedings of the 2003 international workshop on System-level interconnect prediction
Year:
2003

Citing 5
Cited 3

A generic architecture for on-chip packet-switched interconnections

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
Computer Networking: A Top-Down Approach Featuring the Internet

Computer Networking: A Top-Down Approach Featuring the Internet
Design and Analysis of Power Integrity in Deep Submicron System-on-Chip Circuits

Analog Integrated Circuits and Signal Processing
Guaranteeing the quality of services in networks on chip

Networks on chip

NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods

Proceedings of the 2004 international workshop on System level interconnect prediction
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a Network-on-Chip (NoC) architecture was proposed by different authors [1][5][6]. NoC uses Interconnect Intellectual Property (IIP) to connect different resources. In a bottom up approach, this paper first studies the NoC system parameters constrained by the interconnections. Predictions on scaled system parameters such as clock frequency, resource size, global communication bandwidth and inter-resource delay are made for future technologies. Based on these parameters, a global wire planning scheme is proposed. At last, the main IIP modules are described and one possible transmission scheme is demonstrated and simulated.