LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Effects of global interconnect optimizations on performance estimation of deep submicron design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
System level interconnect design for network-on-chip using interconnect IPs
Proceedings of the 2003 international workshop on System-level interconnect prediction
A 1.3GHz fifth generation SPARC64 microprocessor
Proceedings of the 40th annual Design Automation Conference
Interfacing Cores with On-chip Packet-Switched Networks
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI)
Proceedings of the 2004 international workshop on System level interconnect prediction
Optimization of throughput performance for low-power VLSI interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wiring needs. This paper proposes a low overhead wave-pipelined two-slot time division multiplexed (WP/2-TDM) routing technique that harnesses the inherent intra-clock period wire idleness to implement wire sharing in combination with wave-pipelined circuit techniques. It is illustrated in this paper that WP/2-TDM routing can be readily incorporated into future gigascale integration (GSI) systems to reduce the number of interconnect routing channels in an attempt to contain escalating manufacturing costs. Two case studies, one at the circuit level and one at the system level, are presented to illustrate the advantages of WP/2-TDM routing. The circuit level implementation exhibits more than 40% reduction in wire area, a 30% reduction in silicon area with no increase in dynamic power and no loss of throughput performance.