A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
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With the emergence of the packet-switched networks asa possible system-on-chip (SoC) communicationparadigm, the design of network-on-chips (NoC) hasprovided a challenge to the designers. Meeting latencyrequirements of communication among various cores isone of the crucial objectives for system designers. Thecore interface to the networking logic and thecommunication network are the key contributors tolatency. With the goal of reducing this latency weexamine the packetization strategies in the NoCcommunication. In this paper, three schemes ofimplementations are analyzed, and the costs in terms oflatency, and area are projected through actual synthesis.