Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Prediction of interconnect pattern density distribution: derivation, validation, and applications
Proceedings of the 2003 international workshop on System-level interconnect prediction
Interfacing Cores with On-chip Packet-Switched Networks
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In many wire-limited VLSI digital systems the time delay of the longest global interconnect can be a significant percentage of the clock period. However, because semi-global and global wires with shorter wire lengths can have a much smaller time delay, they can remain idle (i.e. not switching) for a significant portion of the clock period even after their data has been transmitted. To capitalize on this phenomenon, this paper proposes that a low-overhead 2-slot Time Division Multiplexing (TDM) network should be incorporated into the multilevel interconnect architectures of future GSI systems to help reduce the escalating manufacturing costs that are primarily due to the projected increase in the number of metal layers. Using system-level interconnect prediction (SLIP) techniques, it is shown that a 20% reduction in the number of metal levels could be achieved for a 100M transistor VLSI system with only a 5-10% increase in power dissipation.