Turbo codes: principles and applications
Turbo codes: principles and applications
An efficient architecture model for systematic design of application-specific multiprocessor SoC
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interfacing Cores with On-chip Packet-Switched Networks
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
MaRS: a macro-pipelined reconfigurable system
Proceedings of the 1st conference on Computing frontiers
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
MAIA: a framework for networks on chip generation and verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Core Network Interface Architecture and Latency Constrained On-Chip Communication
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Increasing the throughput of an adaptive router in network-on-chip (NoC)
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A high level power model for Network-on-Chip (NoC) router
Computers and Electrical Engineering
A Low-Latency and Memory-Efficient On-chip Network
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Parallel processing for block ciphers on a fault tolerant networked processor array
International Journal of High Performance Systems Architecture
CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems
Proceedings of the Conference on Design, Automation and Test in Europe
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Recently Network-on-Chip (NoC) technique has been proposed as a promising solution for on-chip interconnection network. However, different interface specification of integrated components raises a considerable difficulty for adopting NoC techniques. In this paper, we present a generic architecture for network interface (NI) and associated wrappers for a networked processor array (NoC based multiprocessor SoC) in order to allow systematic design flow for accelerating the design cycle. Case studies for memory and turbo decoder IPs show the feasibility and efficiency of our approach.