MAIA: a framework for networks on chip generation and verification

Authors:
Luciano Ost;Aline Mello;José Palma;Fernando Moraes;Ney Calazans
Affiliations:
FACIN-PUCRS, Porto Alegre, Brazil;FACIN-PUCRS, Porto Alegre, Brazil;II - UFRGS, Porto Alegre - Brazil;FACIN-PUCRS, Porto Alegre, Brazil;FACIN-PUCRS, Porto Alegre, Brazil
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

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Abstract

The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be developed to integrate NoC interconnection architectures and IP cores into SoCs. Such tools have to fulfill three main requirements: (i) automated NoC generation; (ii) automated production of NoC-IP core interfaces; (iii) seamless analysis of NoC traffic parameters. The objective of this paper is to present the MAIA framework, which includes functions to address all these requirements. NoCs generated by the MAIA framework have been used to successfully prototype SoCs in FPGAs.