CAFES: A framework for intrachip application modeling and communication architecture design

Authors:
César Marcon;Ney Calazans;Edson Moreno;Fernando Moraes;Fabiano Hessel;Altamiro Susin
Affiliations:
Faculty of Informatics, Pontifical Catholic University of Rio Grande do Sul, Porto Alegre, Brazil;Faculty of Informatics, Pontifical Catholic University of Rio Grande do Sul, Porto Alegre, Brazil;Faculty of Informatics, Pontifical Catholic University of Rio Grande do Sul, Porto Alegre, Brazil;Faculty of Informatics, Pontifical Catholic University of Rio Grande do Sul, Porto Alegre, Brazil;Faculty of Informatics, Pontifical Catholic University of Rio Grande do Sul, Porto Alegre, Brazil;Electrical Engineering Department, Federal University of Rio Grande do Sul, Porto Alegre, Brazil
Venue:
Journal of Parallel and Distributed Computing
Year:
2011

Citing 23
Cited 1

Simulated annealing: theory and applications

Simulated annealing: theory and applications
TGFF: task graphs for free

Proceedings of the 6th international workshop on Hardware/software codesign
Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
Analysis of power consumption on switch fabrics in network routers

Proceedings of the 39th annual Design Automation Conference
Tabu Search

Tabu Search
Billion-Transistor Architectures

Computer
Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints

Proceedings of the conference on Design, automation and test in Europe - Volume 1
Bandwidth-Constrained Mapping of Cores onto NoC Architectures

Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip

Proceedings of the conference on Design, automation and test in Europe - Volume 2
SUNMAP: a tool for automatic topology selection and generation for NoCs

Proceedings of the 41st annual Design Automation Conference
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
HERMES: an infrastructure for low area overhead packet-switching networks on chip

Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Models for Embedded Application Mapping onto NoCs: Timing Analysis

RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
Energy-aware mapping for tile-based NoC architectures under performance constraints

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Time and energy efficient mapping of embedded applications onto NoCs

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
MAIA: a framework for networks on chip generation and verification

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Inserting Data Encoding Techniques into NoC-Based Systems

ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Communication-aware stochastic allocation and scheduling framework for conditional task graphs in multi-processor systems-on-chip

EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
High-Level Estimation of Execution Time and Energy Consumption for Fast Homogeneous MPSoCs Prototyping

RSP '08 Proceedings of the 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping
A Fast Emulation-Based NoC Prototyping Framework

RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration

VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Architectural energy optimization by bus splitting

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Partitioning and mapping on NoC-Based MPSoC: an energy consumption saving approach

Proceedings of the 4th International Workshop on Network on Chip Architectures

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes CAFES, an extensible, open-source framework supporting several tasks related to high-level modeling and design of applications employing complex intrachip communication infrastructures. CAFES comprises several built-in models, including application, communication architecture, energy consumption and timing models. It also includes a set of generic and specific algorithms and additional supporting tools, which jointly with the cited models allow the designer to describe and evaluate applications requirements and constraints on specified communication architectures. Several examples of the use of CAFES underline the usefulness of the framework. Some of these are approached in this paper: (i) a realistic application captured at high-level that has its computation time estimated after mapping at the clock cycle level; (ii) a multi-application system that is automatically mapped to a large intrachip network with related tasks occupying contiguous areas in the chip layout; (iii) a set of mapping algorithms explored to define trade-offs between run time and energy savings for small to large intrachip communication architectures.