Billion-Transistor Architectures

Authors:
Doug Burger;James R. Goodman
Affiliations:
-;-
Venue:
Computer
Year:
1997

Citing 1
Cited 25

The Future of Microprocessors

IEEE Micro

Initial results on the performance and cost of vector microprocessors

MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Simple vector microprocessors for multimedia applications

MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
A dynamic scheduling logic for exploiting multiple functional units in single chip multithreaded architectures

Proceedings of the 1999 ACM symposium on Applied computing
Computer Vision Algorithms on Reconfigurable Logic Arrays

IEEE Transactions on Parallel and Distributed Systems
Trident: a scalable architecture for scalar, vector, and matrix operations

CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
Exploring performance tradeoffs for clustered VLIW ASIPs

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A New Direction for Computer Architecture Research

Computer
Guest Editors' Introduction: Early 21st Century Processors

Computer
Instruction Level Distributed Processing: Adapting to Future Technology

ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing
A Two Dimensional Vector Architecture for Multimedia

Euro-Par '01 Proceedings of the 7th International Euro-Par Conference Manchester on Parallel Processing
Heterogeneous Clustered Processors: Organisation and Design

Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Mapping of DSP Algorithms on Field Programmable Function Arrays

FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
FCCMS and the Memory Wall

FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
LLVA: A Low-level Virtual Instruction Set Architecture

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Two-level branch prediction using neural networks

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Billion-Transistor Architectures: There and Back Again

Computer
Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors

IEEE Transactions on Parallel and Distributed Systems
Instruction Replication for Reducing Delays Due to Inter-PE Communication Latency

IEEE Transactions on Computers
Access region cache with register guided memory reference partitioning

Journal of Systems Architecture: the EUROMICRO Journal
Effect of increasing chip density on the evolution of computer architectures

IBM Journal of Research and Development
Product families on-chip: combining the software product family paradigm with run-time reprogrammable hardware technology

COMPSAC-W'05 Proceedings of the 29th annual international conference on Computer software and applications conference
Low Power Design for a Multi-core Multi-thread Microprocessor

GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
CAFES: A framework for intrachip application modeling and communication architecture design

Journal of Parallel and Distributed Computing
Understanding prediction limits through unbiased branches

ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Dynamic partition of memory reference instructions – a register guided approach

Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing

Quantified Score

Hi-index	4.11

Visualization

Abstract

First Page of the Article