High Performance Compilers for Parallel Computing
High Performance Compilers for Parallel Computing
Billion-Transistor Architectures
Computer
Asynchronous First-in First-out Queues
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
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The rapid development of electronic technology and new trends in the software market are forcing micro-architects to explore new solutions to improve performance and reliability. In this paper, we describe the idea of Heterogeneous Clustered Processors as a viable alternative to well known proposals for future billion-transistor processors. The architectural model is described together with a test core and its preliminary performance evaluation.