Kin: a high performance asynchronous processor architecture
ICS '98 Proceedings of the 12th international conference on Supercomputing
Deep-Submicron Microprocessor Design Issues
IEEE Micro
Heterogeneous Clustered Processors: Organisation and Design
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Single-rail handshake circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
An Asynchronous Low-Power 80C51 Microcontroller
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
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Improving processor performance pushes designers to look for every possible design alternative. Moreover, the need for embedded processing cores exhibiting low power consumption and reduced EM noise is leading to changes in system design. This trend has suggested the adoption of self-timed systems, whose energy and noise characteristics depend upon the processed data and the processing rate. In this paper, we explore the design space of first-in first-output queues, which are fundamental component in most recent proposals for asynchronous processors. Different strategies have been refined and evaluated using the handshake circuits methodology.