Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The tangram framework (embedded tutorial): asynchronous circuits for low power
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Transformations for the synthesis and optimization of asynchronous distributed control
Proceedings of the 38th annual Design Automation Conference
Implementing asynchronous circuits using a conventional EDA tool-flow
Proceedings of the 39th annual Design Automation Conference
Logic Synthesis and Verification
Asynchronous First-in First-out Queues
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
A New Methodology to Design Low-Power Asynchronous Circuits
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Building Asynchronous Circuits with JBits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
High-level synthesis of asynchronous systems by data-driven decomposition
Proceedings of the 40th annual Design Automation Conference
Memory Faults in Asynchronous Microprocessors
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A Coarse-Grain Phased Logic CPU
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Design of a cell library for asynchronous microengines
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A Coarse-Grain Phased Logic CPU
IEEE Transactions on Computers
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic placement of micropipeline standard cells
WSEAS Transactions on Circuits and Systems
Avoiding Irreducible CSC Conflicts by Internal Communication
Fundamenta Informaticae - Application of Concurrency to System Design
Asynchronous DSP for low-power energy-efficient embedded systems
Microprocessors & Microsystems
Power reduction of asynchronous logic circuits using activity detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling
Microelectronics Journal
An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology
Journal of Electronic Testing: Theory and Applications
A low-latency adaptive asynchronous interconnection network using bi-modal router nodes
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Low power techniques applied to a 80c51 microcontroller for high temperature applications
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Design of asynchronous embedded processor with new ternary data encoding scheme
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Avoiding Irreducible CSC Conflicts by Internal Communication
Fundamenta Informaticae - Application of Concurrency to System Design
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This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 \mu CMOS process and it shows a power advantage of a factor 4 compared to a recent synchronous implementation in the same technology. The chip is fully bit compatible with the synchronous implementation, and timing compatible for external memory access. The circuit is a compiled VLSI-program, using Tangram as VLSI-programming language and the Tangram tool-set to compile the design automatically to a standard-cell netlist. This design approach proves to be powerful enough to describe the microcontroller and derive an efficient implementation. Further, it offers the designer the possibility to explore various alternatives in the design space.