Unifying synchronous/asynchronous state machine synthesis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Low-Power, Low-Noise, Configurable Self-Timed DSP
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
An Asynchronous Low-Power 80C51 Microcontroller
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
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This paper presents the design of an asynchronous DSP that is code compatible with the Motorola DSP56000, with the objective of low power and high energy efficiency to extend the lifespan of the batteries in embedded systems embodying the DSP. It features a unified and low-overhead pipeline flush design, a common-case oriented and efficient single-instruction repeating design, and retimed and single-cycle address generation. The asynchronous DSP is implemented using 130nm CMOS process and is completely standard-cell based. Pre-layout simulation results demonstrate an equivalent speed of 61.5 MIPS and energy dissipation of 54.5@mW/MIPS @ 1.2V running a Radix 2 FFT benchmark program, and a 30.0% energy reduction compared to the clock-gated synchronous counterpart.