Communications of the ACM
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Testability of asynchronous timed control circuits with delay assumptions
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Automatic technology mapping for generalized fundamental-mode asynchronous designs
DAC '93 Proceedings of the 30th international Design Automation Conference
Automatic synthesis of burst-mode asynchronous controllers
Automatic synthesis of burst-mode asynchronous controllers
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
The Post Office experience: designing a large asynchronous chip
Integration, the VLSI Journal - Special issue on asynchronous systems
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Decomposition methods for library binding of speed-independent asynchronous designs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Testing redundant asynchronous circuits by variable phase splitting
EURO-DAC '94 Proceedings of the conference on European design automation
Modeling and synthesis of timed asynchronous circuits
EURO-DAC '94 Proceedings of the conference on European design automation
CAD tools for the synthesis, verification, and testability of robust asynchronous circuits
CAD tools for the synthesis, verification, and testability of robust asynchronous circuits
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis of hazard-free customized CMOS complex-gate networks under multiple-input changes
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Lazy transition systems: application to timing optimization of asynchronous circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A generalized state assignment theory for transformation on signal transition graphs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Automatic synthesis of 3D asynchronous state machines
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Hazard-non-increasing gate-level optimization algorithms
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An efficient divide and conquer algorithm for exact hazard free logic minimization
Proceedings of the conference on Design, automation and test in Europe
Transformations for the synthesis and optimization of asynchronous distributed control
Proceedings of the 38th annual Design Automation Conference
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools
Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools
Algorithms for Synthesis and Testing of Asynchronous Circuits
Algorithms for Synthesis and Testing of Asynchronous Circuits
UCLOCK: Automated Design of High-Peformance Unclocked State Machines
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Automatic Synthesis of Fast Compact Asynchronous Control Circuits
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
General Conditions for the Decomposition of State-Holding Elements
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Complete State Encoding Based on the Theory of Regions
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Optimizing average-case delay in technology mapping of burst-mode circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A FIFO Ring Performance Experiment
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
AMULET2e: An Asynchronous Embedded Controller
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Low-Power, Low-Noise, Configurable Self-Timed DSP
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Average-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
An Asynchronous Low-Power 80C51 Microcontroller
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
High-Level Asynchronous System Design Using the ACK Framework
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous Design Using Commercial HDL Synthesis Tools
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
FLEETzero: An Asynchronous Switching Experiment
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Efficient Exact Two-Level Hazard-Free Logic Minimization
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Synthesis of asynchronous controllers for heterogeneous systems
Synthesis of asynchronous controllers for heterogeneous systems
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast heuristic and exact algorithms for two-level hazard-free logic minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decomposition and technology mapping of speed-independent circuits using Boolean relations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact two-level minimization of hazard-free logic with multiple-input changes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
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Asynchronous, or clockless, design is receiving renewed attention, due to its potential benefits of modularity, low power, low electromagnetic interference and average-case performance. This chapter focuses on two styles for asynchronous controller synthesis: speed-independent and burst-mode. Basic synthesis and optimization methods are presented, as well as an introduction to timing-based optimization.