Symbolic hazard-free minimization and encoding of asynchronous finite state machines
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Logic Synthesis and Verification
Control Resynthesis for Control-Dominated Asynchronous Designs
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Synthesis for Logical Initializability of Synchronous Finite State Machines
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Concurrent Error Detection in Asynchronous Burst-Mode Controllers
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
FPGA glitch power analysis and reduction
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
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We describe a new method for directly synthesizing a hazard-free multilevel logic implementation from a given logic specification. The method is based on free/ordered Binary Decision Diagrams (BDD's), and is naturally applicable to multiple-output logic functions. Given an incompletely-specified (multiple-output) Boolean function, the method produces a multilevel logic network that is hazard-free for a specified set of multiple-input changes. We assume an arbitrary (unbounded) gate and wire delay model under a pure delay (PD) assumption, we permit multiple-input changes, and we consider both static and dynamic hazards under the fundamental-mode assumption. Our framework is thus general and powerful. While it is not always possible to generate hazard-free implementations using our technique, we show that in some cases hazard-free multilevel implementations can be generated when hazard-free two-level representations cannot be found. This problem is generally regarded as a difficult problem and it has important applications in the field of asynchronous design. The method has been automated and applied to a number of examples