Initializability Consideration in Sequential Machine Synthesis
IEEE Transactions on Computers
Minimum length synchronizing sequences of finite state machine
DAC '93 Proceedings of the 30th international Design Automation Conference
Hazard-non-increasing gate-level optimization algorithms
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Initialization Isuues in the Synthesis of Asynchronous Circuits
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Synthesis-for-Initializability of Asynchronous Sequential Machines
Proceedings of the IEEE International Test Conference on Test and Design Validity
On the Initialization of Sequential Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Hazard detection in combinational and sequential switching circuits
IBM Journal of Research and Development
Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact two-level minimization of hazard-free logic with multiple-input changes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a new method for the synthesis for logical initializability of synchronous state machines. The goal is to produce a gate-level implementation that is initializable when simulated by a 3-valued (0,1,X) simulator. We build on the approach of Cheng and Agrawal (1989,92) who constrain state assignment to translate functional initializability into logic initializability. We propose an alternative method which is guaranteed safe and not as conservative. In addition, we propose necessary and sufficient conditions on 2-level and multi-level logic synthesis to insure 3-valued simulation succeeds.