Estimation and bounding of energy consumption in burst-mode control circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Symbolic hazard-free minimization and encoding of asynchronous finite state machines
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Espresso-HF: a heuristic hazard-free minimizer for two-level logic
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Synthesis of hazard-free customized CMOS complex-gate networks under multiple-input changes
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Automatic synthesis of extended burst-mode circuits using generalized C-elements
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Synthesis of low-power asynchronous circuits in a specified environment
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Cluster-cover: a theoretical framework for a class of VLSI-CAD optimization problems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Asynchronous interface specification, analysis and synthesis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Logic Synthesis and Verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Optimizing average-case delay in technology mapping of burst-mode circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
On the Existence of Hazard-Free Multi-Level Logic
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Synthesis for Logical Initializability of Synchronous Finite State Machines
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Concurrent Error Detection in Asynchronous Burst-Mode Controllers
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines
IEEE Transactions on Computers
Soft-error tolerance and mitigation in asynchronous burst-mode circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-rail asynchronous logic multi-level implementation
Integration, the VLSI Journal
A Novel Formalism for Partially Defined Asynchronous Feedback Digital Circuits
Journal of Electronic Testing: Theory and Applications
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This paper describes a new method for exact hazard-free logic-minimization of Boolean functions. Given an incompletely-specified Boolean function, the method produces a minimum-cost sum-of-products implementation which is hazard-free for a given set of multiple-input changes, if such a solution exists. The method is a constrained version of the Quine-McCluskey algorithm. It has been automated and applied to a number of examples. Results are compared with results of a comparable non-hazard-free method (espresso-exact). Overhead due to hazard elimination is shown to be negligible