Combinatorics on traces
Scheduling parallel tasks with individual deadlines
Theoretical Computer Science
Timed Petri Nets in Hybrid Systems: Stability and SupervisoryControl
Discrete Event Dynamic Systems
Local Checking of Trace Synchroniziability
MFCS '88 Proceedings of the Mathematical Foundations of Computer Science 1988
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Minimal schedulability interval for real-time systems of periodic tasks with offsets
Theoretical Computer Science
Topology for Computing (Cambridge Monographs on Applied and Computational Mathematics)
Topology for Computing (Cambridge Monographs on Applied and Computational Mathematics)
Optimal infinite scheduling for multi-priced timed automata
Formal Methods in System Design
Abstractions for hybrid systems
Formal Methods in System Design
Fault Diagnosis of Discretely Controlled Continuous Systems by Means of Discrete-Event Models
Discrete Event Dynamic Systems
Logic Functions and Equations: Examples and Exercises
Logic Functions and Equations: Examples and Exercises
A barcode shape descriptor for curve point cloud data
Computers and Graphics
STG decomposition strategies in combination with unfolding
Acta Informatica
STG Decomposition: Internal Communication for SI Implementability
ACSD '10 Proceedings of the 2010 10th International Conference on Application of Concurrency to System Design
Metastability and Synchronizers: A Tutorial
IEEE Design & Test
Improved Parallel Composition of Labelled Petri Nets
ACSD '11 Proceedings of the 2011 Eleventh International Conference on Application of Concurrency to System Design
Exact two-level minimization of hazard-free logic with multiple-input changes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In contrast to combinational logic and master clocked sequential logical, asynchronous feedback circuits are partially defined due to analogous meta-stabilities. We present a novel formalism to exactly explore this digitally assisted analog phenomenon in order to build up a representative test bench that is able to enforce race constraints (meta-stable behavior) for non-deterministics, instabilities as well as for oscillations in feedback structures. Further, we introduce our definitions for consistently modeling under state transition graphs, we provide all entities for modeling asynchronous feedback structures and state our proposed methodology with an exemplary asynchronous circuitry. The given example is explained at a high level of abstraction, all data for revision is provided, too. The approach seems to be capable to test for meta-stabilities, analog behavior in feedback digital structures.