Randomized rounding: a technique for provably good algorithms and algorithmic proofs
Combinatorica - Theory of Computing
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A framework for satisfying input and output encoding constraints
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Modeling and comparing CMOS implementations of the C-element
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools
Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools
Fsimac: a fault simulator for asynchronous sequential circuits
ATS '00 Proceedings of the 9th Asian Test Symposium
Formal Methods in System Design
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
SPIN-TEST: automatic test pattern generation for speed-independent circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic
IEEE Transactions on Computers
Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines
IEEE Transactions on Computers
Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits
IEEE Transactions on Computers
Hazard detection in combinational and sequential switching circuits
IBM Journal of Research and Development
Synthesis for testability techniques for asynchronous circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing to radiation harden combinational logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact two-level minimization of hazard-free logic with multiple-input changes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We discuss the problem of soft errors in asynchronous burst-mode machines (ABMMs), and we propose two solutions. The first solution is an error tolerance approach, which leverages the inherent functionality of Muller C-elements, along with a variant of duplication, to suppress all transient errors. The proposed method is more robust and less expensive than the typical triple modular redundancy error tolerance method and often even less expensive than previously proposed concurrent error detection methods, which only provide detection but no correction. The second solution is an error mitigation approach, which leverages a newly devised soft-error susceptibility assessment method for ABMMs, along with partial duplication, to suppress a carefully chosen subset of transient errors. Three progressively more powerful options for partial duplication select among individual gates, complete state/output logic cones, or partial state/output logic cones and enable efficient exploration of the tradeoff between the achieved soft-error susceptibility reduction and the incurred area overhead. Furthermore, a gate-decomposition method is developed to leverage the additional soft-error susceptibility reduction opportunities arising during conversion of a two-level ABMM implementation into a multilevel one. Extensive experimental results on benchmark ABMMs assess the effectiveness of the proposed methods in reducing soft-error susceptibility, and their impact on area, performance, and offline testability.