The Design and Use of Hazard-Free Switching Networks
Journal of the ACM (JACM)
Application of Ternary Algebra to the Study of Static Hazards
Journal of the ACM (JACM)
Uncertainty, Energy, and Multiple-Valued Logics
IEEE Transactions on Computers
A characterization of ternary simulation of gate networks
IEEE Transactions on Computers
A new approach to derive robust sets for stuck-open faults in CMOS combinational logic circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Boolean process-an analytical approach to circuit representation (II)
ATS '95 Proceedings of the 4th Asian Test Symposium
Limitations of VLSI implementation of delay-insensitive codes
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Microprogrammed operations for a three-value logic simulator
MICRO 7 Conference record of the 7th annual workshop on Microprogramming
A graph approach to DFT hardware placement for robust delay fault BIST
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Synthesis for Logical Initializability of Synchronous Finite State Machines
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
The Partition Method for the Order - Insensitivity in a Synchronous Distributed Systems
ISCC '00 Proceedings of the Fifth IEEE Symposium on Computers and Communications (ISCC 2000)
Design for Testability A Survey
IEEE Transactions on Computers
A Unified Approach to Combinational Hazards
IEEE Transactions on Computers
A Nine-Valued Circuit Model for Test Generation
IEEE Transactions on Computers
A Heuristic Algorithm for the Testing of Asynchronous Circuits
IEEE Transactions on Computers
Equivalence of the Arbiter, the Synchronizer, the Latch, and the Inertial Delay
IEEE Transactions on Computers
On the Three-Valued Simulation of Digital Systems
IEEE Transactions on Computers
A Simplified General Method for Static Hazard Detection
IEEE Transactions on Computers
Functional Partitioning and Simulation of Digital Circuits
IEEE Transactions on Computers
Modeling and Digital Simulation for Design Verification and Diagnosis
IEEE Transactions on Computers
Logic Properties of Unate Discrete and Switching Functions
IEEE Transactions on Computers
Simulation of gate circuits in the algebra of transients
CIAA'02 Proceedings of the 7th international conference on Implementation and application of automata
Hazard-based detection conditions for improved transition fault coverage of scan-based tests
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Initialization-based test pattern generation for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hazard-based detection conditions for improved transition path delay fault coverage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Constructive semantics for instantaneous reactions
Theoretical Computer Science
Test generation for MOS circuits
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Soft-error tolerance and mitigation in asynchronous burst-mode circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using three-valued logic to specify and verify algorithms of computational geometry
ICFEM'05 Proceedings of the 7th international conference on Formal Methods and Software Engineering
Ternary simulation: refinement of binary functions or abstraction of real-time behaviour?
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
Constructive Boolean circuits and the exactness of timed ternary simulation
Formal Methods in System Design
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Various types of counter models have been treated in the literature over the past twenty years. In all these models the counter mechanism involves a fixed or random dead time following a registered event. In this paper a different type of counter mechanism ...