An experimental MOS fault simulation program CSASIM
DAC '84 Proceedings of the 21st Design Automation Conference
Three levels of accuracy for the simulation of different fault types in digital systems
DAC '75 Proceedings of the 12th Design Automation Conference
9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits
IEEE Transactions on Computers
A Nine-Valued Circuit Model for Test Generation
IEEE Transactions on Computers
Vector Boolean Algebra and Calculus
IEEE Transactions on Computers
Multiple-Valued Logic its Status and its Future
IEEE Transactions on Computers
A Note on Three-Valued Logic Simulation
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
Hazard detection in combinational and sequential switching circuits
IBM Journal of Research and Development
Deriving Logic Systems for Path Delay Test Generation
IEEE Transactions on Computers
Interactive digital-simulation laboratory gains special components
CSC '87 Proceedings of the 15th annual conference on Computer Science
Timing Analysis of Combinational Circuits in Intuitionistic Propositional Logic
Formal Methods in System Design
G-vector: A New Model for Glitch Analysis in Logic Circuits
Journal of VLSI Signal Processing Systems
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The multiple-valued logics obtained by introducing uncertainty and energy considerations into classical switching theory are studied in this paper. First, the nature of uncertain or unknown signals is examined, and two general uncertainty types called U-values and P-values are identified. It is shown that multiple-valued logics composed of U/P-values can be systematically derived from 2-valued Boolean algebra. These are useful for timing and hazard analysis, and provide a rigorous framework for designing gate-level logic simulation programs. Next, signals of the form (v, s) are considered where v and s denote logic level and strength, respectively, and the product vs corresponds to energy flow or power. It is shown that these signals form a type of lattice called a pseudo-Boolean algebra. Such algebras characterize the behavior of digital circuits at a level (the switch level) intermediate between the conventional analog and logical levels. They provide the mathematical basis for an efficient new class of switch-level simulation programs used in MOS VLSI design.